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1 features ? low-voltage and standard-voltage operation ?1.8v (v cc = 1.8v to 3.6v) ?2.5v (v cc = 2.5v to 3.6v) ? internally organized 65,536 x 8 ? two-wire serial interface ? schmitt triggers, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 1 mhz (3.6v), 400 khz (1.8v, 2.5v) compatibility ? write protect pin for hardware and software data protection ? 128-byte page write mode (partial page writes allowed) ? self-timed write cycle (5 ms max) ? high reliability ? endurance: 1,000,000 write cycles ? data retention: 40 years ? lead-free/halogen-free devices ? 8-lead pdip, 8-lead jedec so ic, 8-lead eiaj soic, 8-lead tssop, 8-ball dbga2, and 8-lead ultra thin small array (sap) packages ? die sales: wafer form, waffle pack and bumped die description the at24c512b provides 524,288 bits of se rial electrically erasable and programma- ble read only memory (eeprom) organized as 65,536 words of 8 bits each. the device?s cascadable feature allows up to ei ght devices to share a common two-wire bus. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the devices are available in space-saving 8-pin pdip, 8-lead jedec soic, 8-lead eiaj soic, 8-lead tssop, 8-ball dbga2 and 8-lead ultra thin sap packages. in addition, the entire family is available in a 1.8v (1.8v to 3.6v) version. table 1. pin configurations pin name function a0?a2 address inputs sda serial data scl serial clock input wp write protect rev. 5112d?seepr?3/07 two-wire serial eeprom 512k (65,536 x 8) at24c512b with three device address inputs preliminary 8-lead pdip 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 a2 g nd vc c wp sc l sd a 8-lead ultra thin sap bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda a0 a1 a2 gnd 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-ball dbga2 bottom view 1 2 3 4 8 7 6 5 vcc wp s cl s da a0 a1 a2 gnd
2 at24c512b [preliminary] 5112d?seepr?3/07 figure 1. block diagram absolute maximum ratings* operating temperature..................................?55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65 c to +150 c voltage on any pin with respect to ground .............. ...................... ?1.0v to +7.0v maximum operating voltage ............................................ 4.3v dc output current........................................................ 3.0 ma
3 at24c512b [preliminary] 5112d?seepr?3/07 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/page addresses (a2, a1, a0): the a2, a1, and a0 pins are device address inputs that are hardwir ed (directly to gnd or to v cc) for compatibility with other at24cxx devices. when the pins are hardwir ed, as many as eight 512k devices may be addressed on a single bus system. (device addressing is discussed in detail under ?device addressing,? page 8.) a device is selected when a corresponding hardware and software match is true. if these pins are left floating, the a2, a1, and a0 pins will be internally pulled down to gnd. however, due to capacitive coupling that may appear during customer applications, atmel ? recommends always connecting the address pins to a known state. when using a pull-up resistor, atmel recommends using 10k ? or less. write protect (wp): the write protect input, when connected to gnd, allows nor- mal write operations. when wp is connected dire ctly to vcc, all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled down to gnd. however, due to capacitive couplin g that may appear during customer applica- tions, atmel recommends always connecting t he wp pins to a known state. when using a pull-up resistor, atmel recommends using 10k ? or less. memory organization at24c512b, 512k serial eeprom: the 512k is internally organized as 512 pages of 128-bytes each. random word addressing requires a 16-bit data word address.
4 at24c512b [preliminary] 5112d?seepr?3/07 note: 1. this parameter is characterized and is not 100% tested. table 3. dc characteristics note: 1. v il min and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from: t a = 25 c, f = 1.0 mhz, v cc = +1.8v to +3.6v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +3.6v (unless otherwise noted) symbol parameter test co ndition min typ max units v cc1 supply voltage 1.8 3.6 v i cc1 supply current v cc = 3.6v read at 400 khz 1.0 2.0 ma i cc2 supply current v cc = 3.6v write at 400 khz 2.0 3.0 ma i sb1 standby current (1.8v option) v cc = 1.8v v in = v cc or v ss 1.0 a v cc = 3.6v 3.0 a i sb2 standby current (2.5v option) v cc = 2.5v v in = v cc or v ss 2.0 a v cc = 3.6v 3.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ? 0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 at24c512b [preliminary] 5112d?seepr?3/07 table 4. ac characteristics (industrial temperature) notes: 1. this parameter is ensured by characterization. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.5v, 3.6v), 10 k ? (1.8v) input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5 v cc device operation clock and data transitions: the sda pin is normally pulled high with an exter- nal device. data on the sda pin may change only during scl low time periods (see figure 4 on page 7). data c hanges during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 5 on page 7). stop condition: a low-to-high transition of sda wit h scl high is a stop condition. after a read sequence, the stop command will place th e eeprom in a standby power mode (see figure 5 on page 7). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero du ring the ninth clock cycle to acknowledge that it has received each word. applicable over recommended operating range from t ai = ? 40 c to +85 c, v cc = +1.8v to +3.6v, cl = 100 pf (unless oth- erwise noted). test conditions are listed in note 2. symbol parameter 1.8-volt, 2.5-volt 3.6-volt units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.3 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time (1) 100 50 ns t aa clock low to data out valid 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 1.3 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start set-up time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in set-up time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 300 100 ns t su.sto stop set-up time 0.6 0.25 s t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 25c, page mode, 3.3v 1,000,000 write cycles
6 at24c512b [preliminary] 5112d?seepr?3/07 standby mode: the at24c512b features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. software reset: after an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) create a st art bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. the device is ready for next communication after above steps have been completed. figure 1. protocol reset condition figure 2. bus timing (scl: serial clock, sda: serial data i/o) s tart bit s top bit s tart bit dummy clock cycles s cl s da 12 38 9
7 at24c512b [preliminary] 5112d?seepr?3/07 figure 3. write cycle timing (scl: serial clock, sda: serial data i/o) note: 1. the writ e cycle time t wr is the time from a valid stop condition of a writ e sequence to the end of the internal clear/write cycle. figure 4. data validity figure 5. start and stop definition t wr (1) stop condition start condition wordn ack 8th bit s cl s da
8 at24c512b [preliminary] 5112d?seepr?3/07 figure 6. output acknowledge device addressing the 512k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see figure 7 on page 9). the device address word consists of a mandatory ?1?, ?0 ? sequence for the first four most significant bits as shown. this is commo n to all two-wir e eeprom devices. the 512k uses the three device address bits a2, a1, a0 to allow as many as eight devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a2, a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the r ead/write operation select bit. a read opera- tion is initiated if this bit is high and a writ e operation is initiated if this bit is low. upon a compare of the device address, th e eeprom will output a ?0?. if a compare is not made, the devi ce will return to a standby state. data security: the at24c512b has a hardware data protection scheme that allows the user to write protect the whol e memory when the wp pin is at v cc . write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a ?0? and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a ?0?. the add ressing device, such as a microcontroller, then must term inate the write sequence with a stop condition. at this time the eeprom enters an inte rnally-timed wr ite cycle, t wr , to the nonvolatile memory. all inputs are disabled during this writ e cycle and the eeprom will not respond until the write is complete (see figure 8 on page 10). page write: the 512k eeprom is capabl e of 128-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data wo rd is clocked in. instead, after the eeprom acknowledges receipt of the fi rst data word, the microcontrol ler can transmit up to 127 more data words. the eeprom will respond with a ?0? after each data word received. the microcontroller must terminate the page write sequence with a stop condition (see figure 9 on page 10).
9 at24c512b [preliminary] 5112d?seepr?3/07 the data word address lower 7 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 128 data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be ov erwritten. the address roll over during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabl ed, acknowledge polling can be in itiated. this involves send- ing a start condition followed by the dev ice address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ?0?, allowing the read or write se quence to continue. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to ?1?. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by ?1?. this address stays valid between operations as long as the chip power is maintained. the address roll over during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write select bit set to ?1? is clocked in and acknowledged by the eeprom, the current addr ess data word is serially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition (see figure 10 on page 10). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the mi crocontroller must generate another start condition. the microcontroller now initiate s a current address read by sending a device address with the read/write select bit hi gh. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a ?0? but does generate a following stop condition (see figure 11 on page 10). sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontro ller receives a data word, it responds with an acknowledge. as long as the eeprom rece ives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reac hed, the data word address will roll over and the sequential read will continue. the sequential read operat ion is terminated when the microcontroller does not respond with a ?0? but does generat e a following stop condition (see figure 12 on page 11). figure 7. device address m s b 1 0 1 0 a 2 a 1 a 0 r/w l s b
10 at24c512b [preliminary] 5112d?seepr?3/07 figure 8. byte write figure 9. page write figure 10. current address read figure 11. random read
11 at24c512b [preliminary] 5112d?seepr?3/07 figure 12. sequential read
12 at24c512b [preliminary] 5112d?seepr?3/07 notes: 1. ?-b? denotes bulk 2. ?-t? denotes tape and reel. soic = 4k per reel. tssop and dbga2 = 5k per r eel. sap = 3k per reel. eiaj = 2k per reel. 3. available in waffle pack, tape and reel, and wafer form; or der as sl788 for inkless wafer form. bumped die available upon request. please contact serial eeprom marketing. ordering information ordering code voltage package operation range at24c512b-pu (bulk form only) 1.8 8p3 lead-free/halogen-free/ industrial temperature (?40 c to 85 c) at24c512b-pu25 (bulk form only) 2.5 8p3 at24c512bn-sh-b (1) (nipdau lead finish) 1.8 8s1 at24c512bn-sh-t (2) (nipdau lead finish) 1.8 8s1 at24c512bn-sh25-b (1) (nipdau lead finish) 2.5 8s1 at24c512bn-sh25-t (2) (nipdau lead finish) 2.5 8s1 at24c512bw-sh-b (1) (nipdau lead finish) 1.8 8s2 at24c512bw-sh-t (2) (nipdau lead finish) 1.8 8s2 at24c512bw-sh25-b (1) (nipdau lead finish) 2.5 8s2 at24c512bw-sh25-t (2) (nipdau lead finish) 2.5 8s2 at24c512b-th-b (1) (nipdau lead finish) 1.8 8a2 at24c512b-th-t (2) (nipdau lead finish) 1.8 8a2 at24c512b-th25-b (1) (nipdau lead finish) 2.5 8a2 at24c512b-th25-t (2) (nipdau lead finish) 2.5 8a2 at24c512by7-yh-t (2) (nipdau lead finish) 1.8 8y7 at24c512by7-yh25-t (2) (nipdau lead finish) 2.5 8y7 at24c512bu4-uu-t (2) (nipdau lead finish) 1.8 8u4-1 at24c512b-w-11 (3) 1.8 die sale industrial temperature (?40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.200? wide plastic gull wing small outline package (eiaj soic) 8a2 8-lead, 4.4 mm body, plastic thin sh rink small outli ne package (tssop) 8y7 8-lead, 6.00 mm x 4.90 mm body, ultra thin, dual footprint, non-leaded, small array package (sap) 8u4-1 8-ball, die ball grid array package (dbga2) options ?1.8 low-voltage (1.8v to 3.6v) ?2.5 low-voltage (2.5v to 3.6v)
13 at24c512b [preliminary] 5112d?seepr?3/07 packaging information 8p3 ? pdip 2 3 25 orchard parkway s an jose, ca 9 51 3 1 title drawing no. r rev. 8p3 , 8 -lead, 0. 3 00" wide body, plastic dual in-line package (pdip) 01/0 9 /02 8 p 3 b notes: 1. this drawing is for general information only; refer to jedec drawing m s -001, variation ba, for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge g s - 3 . 3 . d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b 3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b 3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.1 9 5 b 0.014 0.01 8 0.022 5 b2 0.045 0.060 0.070 6 b 3 0.0 3 0 0.0 39 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view
14 at24c512b [preliminary] 5112d?seepr?3/07 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado s prings, co 8 0 9 06 title drawing no. r rev. note: 10/7/0 3 8s1 , 8 -lead (0.150" wide body), plastic gull wing s mall outline (jedec s oic) 8s 1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing m s -012, variation aa for proper dimensions, tolerances, datums, etc. a 1. 3 5 ? 1.75 b 0. 3 1 ? 0.51 c 0.17 ? 0.25 d 4. 8 0 ? 5.00 e1 3 . 8 1 ? 3 . 99 e 5.7 9 ? 6.20 e 1.27 b s c l 0.40 ? 1.27 ? 0 ? 8 ? top view end view s ide view e b d a a1 n e 1 c e1 l
15 at24c512b [preliminary] 5112d?seepr?3/07 8s2 - eiaj soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 4/7/06 8s2 d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 0? 8? e 1.27 bsc 4 1 1 n n e e top view top view c c e1 e1 end view end view a a b b l l a1 a1 e e d d side view side view
16 at24c512b [preliminary] 5112d?seepr?3/07 8a2 ? tssop 2325 orch a rd p a rkw a y s a n jo s e, ca 9 5131 title drawing no. r rev. 5/30/02 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d2. 9 0 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.1 9 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8 a2 , 8-le a d, 4.4 mm body, pl as tic thin shrink sm a ll o u tline p a ck a ge (tssop) note s : 1. thi s dr a wing i s for gener a l inform a tion only. refer to jedec dr a wing mo-153, v a ri a tion aa, for proper dimen s ion s , toler a nce s , d a t u m s , etc. 2. dimen s ion d doe s not incl u de mold fl as h, protr us ion s or g a te bu rr s . mold fl as h, protr us ion s a nd g a te bu rr s s h a ll not exceed 0.15 mm (0.006 in) per s ide. 3. dimen s ion e1 doe s not incl u de inter-le a d fl as h or protr us ion s . inter-le a d fl as h a nd protr us ion s s h a ll not exceed 0.25 mm (0.010 in) per s ide. 4. dimen s ion b doe s not incl u de d a m ba r protr us ion. allow ab le d a m ba r protr us ion s h a ll b e 0.08 mm tot a l in exce ss of the b dimen s ion a t m a xim u m m a teri a l condition. d a m ba r c a nnot b e loc a ted on the lower r a di us of the foot. minim u m s p a ce b etween protr us ion a nd a dj a cent le a d i s 0.07 mm. 5. dimen s ion d a nd e1 to b e determined a t d a t u m pl a ne h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indic a tor thi s corner e e
17 at24c512b [preliminary] 5112d?seepr?3/07 8y7 ? utsap 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. 8y7 , 8-lead (6.00 x 4.90 mm body) ultra-thin soic array package (utsap) y7 b 8y7 10/13/05 common dimensions (unit of measure = mm) symbol min nom max note a 0.60 a1 0.00 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 3.30 3.40 3.50 e1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 d1 pin 1 id e1 l b e1 e pin 1 index area a e d a1 a
18 at24c512b [preliminary] 5112d?seepr?3/07 8u4-1 ? dbga2 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. po8u4-1 a 1/5/05 common dimensions (unit of measure = mm) symbol min nom max note 8u4-1, 8-ball, 2.47 x 4.07 mm body, 0.75 mm pitch, small die ball grid array package (dbga2) a 0.81 0.91 1.00 a 1 0.15 0.20 0.25 a 2 0.40 0.45 0.50 b 0.25 0.30 0.35 d 2.47 bsc e 4.07 bsc e 0.75 bsc e1 0.74 ref d 0.75 bsc d1 0.80 ref 5. dimension 'b' is measured at the maximum solder ball diameter. this drawing is for general information only. d a side view top view 8 solder balls bottom view 1 a b c d 2 (e1) e a1 ball pad corner (d1) 5. b a1 a2 d a1 ball pad corner e
19 at24c512b [preliminary] 5112d?seepr?3/07 revision history doc. rev. date comments 5112d 3/2007 removed no connect row from pin configuration table removed note from page 6 replaced figure 4 with the correct figure removed msb and lsb from figures 8-11 added missing figure 12 5112c 1/2007 modify 8-ball dbga2 drawing on page 1 add lines between ordering information table on page 11 remove at24c512bu4-uu25-t offering from ordering information add 2.5v offering delete 2.7v offering add 8y7 package drawing add dbga2 package add at24c512bu4-uu-t to page 1 and ordering information add 2.7v offering and 2.7v characteristics 5112b 7/2006 pg 1 remove preliminary add advance information add eiaj soic part number offering to pg 1 and pg 12 add eiaj pkg drawing changes to ordering information, page 12; replaced 8y4 package with 8y7 (utsap) package drawing page 1 - added ultra thin sap to features and description 5112a 8/2005 initial document release
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